1. Field of the Invention
The present invention relates in general to ferroelectric memories and in particular to such memories that include memory cells including ferroelectric capacitors and arranged in rows and columns to form an array.
2. Statement of the Problem
It is well known that ferroelectric materials are capable of retaining a polarization which can be used to store information in a non-volatile memory. For example, if a strong enough electric field or voltage is placed across a ferroelectric capacitor, when the voltage is removed, a polarization in the direction of the field remains. If the field is then placed across the same capacitor in the opposite direction, the ferroelectric material switches, and when the field is removed, a polarization in the opposite direction remains. Electronic circuits have been designed to associate the polarization in one direction with a digital logic xe2x80x9c1xe2x80x9d state, and polarization in the opposite direction with a logic xe2x80x9c0xe2x80x9d state. See, for example, the circuits described in U.S. Pat. No. 2,876,436 issued Mar. 3, 1959 to J. R. Anderson. Like other integrated circuit memories, these circuits include memory cells arranged in rows and columns, each memory cell including at least one switch, a capacitor having a pair of electrodes, and the memory also including plate lines, sometimes referred to as drive lines, connected to one electrode of the capacitor in each cell, and bit lines connected to the other electrode of the capacitor through the switch. In this disclosure, we shall refer to the xe2x80x9cplatexe2x80x9d line as a xe2x80x9cdrivexe2x80x9d line, as is sometimes done in the art. In the Anderson patent cited above, the switch is a diode. As is known in the art, the switch can be a transistor having a gate, a source and a drain, and the memory includes word lines connected to the control gate of the transistor. See, for example, U.S. Pat. No. 4,873,664 issued Oct. 10, 1989 to S. Sheffield Eaton, Jr. The transistor acts as a switch controlled by its gate to connect the capacitor to the bit line. Information is written into a memory cell by placing either a high or a low voltage on the bit line, turning the transistor on to connect the bit line to the capacitor, and placing a predetermined voltage between the high and low voltage on the drive line. The high voltage causes the memory cell to assume one polarization state, and the low voltage causes the memory cell to assume the opposite polarization state. The memory cell is read by creating a voltage difference between the bit line and drive line, and connecting the bit line to the capacitor via the transistor. If the ferroelectric state changes due to the applied voltage, the bit line will assume a first voltage, and if the ferroelectric state does not switch, then the bit line will assume a second voltage. The bit line voltage is compared to a reference voltage that is about half-way between the first and second voltages; if the bit line voltage is below the reference voltage, a sense amp drives an output low, and if the bit line voltage is above the reference voltage, a sense amp drives an output high. In this way, the state of the ferroelectric capacitor prior to reading determines the output state when the cell is read.
In the above-described memory and other similar conventional ferroelectric memories, the drive line is pulsed. The drive line, being relatively long and connected to the electrodes of many capacitors, has a high capacitance. Thus, it takes a relatively long time for the voltage to rise to its full value, with the result that the time to read and write to the memory is long. To speed up the read and write processes, ferroelectric memories in which the drive line is not pulsed have been developed. See Hiroki Koike et al., xe2x80x9cA 60-ns 1-Mb Nonvolatile Ferroelectric Memory With A Nondriven Cell Plate Line Write/Read Scheme, IEEE Journal of Solid State Circuits, Vol. 31, No. 11, November 1996. Another solution has been to make the drive line parallel to the bit line, so that only one capacitor at a time is pulsed. See the embodiment of FIG. 6 in the Eaton, Jr. patent mentioned above. Segmented drive lines have also been proposed to speed up the drive line cycle and reduce power. See U.S. Pat. No. 5,598,366 issued Jan. 28, 1997 to Kraus et al. However, all these memories have not been successful due to significant disturb problems. xe2x80x9cDisturbxe2x80x9d is a problematic feature of most prior art ferroelectric memories in which xe2x80x9cdisturbxe2x80x9d voltages, usually small in amplitude, are unavoidably applied to non-accessed memory cells, which voltages can change the memory state and thus lead to erroneous readings. For example, in the Koike et al. reference, it is explained that leakage from the bit line and drive line to the nodes of a capacitor that is not accessed can destroy the data. This problem is overcome with a compensation scheme which adds complexity to the memory and slows it down. Thus, the disturb problem has either resulted in memories that have been made more complex and slower to overcome the disturb, as in the Koike et al. reference, or simply have resulted in the design being too unreliable to be successful, such as the Eaton, Jr. patent. Moreover, the average power requirements of such cells remains quite high.
Up until recently, all ferroelectric materials tended to fatigue overtime, and the switching charge decreased to a point where the cell could no longer be read. About ten years ago, a class of materials, called layered superlattice compounds herein, had been discovered that do not fatigue. However, while the switching charge remains relatively stable in these materials, the materials still age, i.e., the magnitude of the first and second voltages generally depends on the history of the memory cell. For example, depending on the history, both the first and second voltages in one reading on a specific cell will differ by some voltage factor from the first and second voltages of a later reading of the same cell; or the hysteresis curve may drift overtime in the order of milliseconds due to redistribution of charge within the capacitor. Thus, while the reference voltage will be between the first and second voltages for one reading, in a later reading both the first and second voltages may be above the reference voltage. This generally results in a misreading of the memory cell. Thus, these memories are not xe2x80x9csafexe2x80x9d in that the reading or sensing of the data is relatively unreliable.
A typical solution to the above problems is disclosed in U.S. Pat. No. 4,888,733 issued Dec. 19, 1989 to Kenneth J. Mobley. The memory disclosed in the Mobley patent isolates the ferroelectric capacitor with two transistors, which avoids the disturb problem. It also pulses the ferroelectric capacitor in one direction and stores the developed charge on a first temporary storage capacitor, pulses the ferroelectric capacitor in the opposite direction and stores the developed charge on a second temporary storage capacitor, and then compares the stored charges on the two storage capacitors. Thus, this memory essentially compares two states of the same capacitor taken one after another in a time interval that is too short for aging or other changes to take place, which avoids the aging problem. However, this solution triples the length of time it takes to read a memory; thus, this memory is not competitive with state-of-the-art memories which require fast read times. Further, the extra temporary storage capacitors are linear capacitors, which take up significant additional room in the memory, so a memory according to the Mobley design is relatively bulky and is not competitive in a memory market where memory chips are increasingly dense. There are many other multi-capacitor/multi-transistor ferroelectric memories that have been proposed to solve the above problems, some of which have been incorporated into commercial products. All of them are both several times more dense and slower than conventional DRAMs.
The above problems, particularly the aging problem and the xe2x80x9cdisturbxe2x80x9d problem, are most severe in the fastest and densest memory architectures. Thus, commercial applications of ferroelectric memories up to now have been limited to relatively slow and bulky architectures, such as the Mobley design. It would be highly desirable to have a ferroelectric memory architecture that was faster and less bulky than the Mobley design, yet was not subject to the problem of disturb. Such a memory design that also avoided the aging problem would be a significant advance in the art.
The invention solves the above problems, as well as other problems of the prior art, by providing a ferroelectric memory in which each memory cell can be individually selected without electrically connecting it to any other memory cell, thus eliminating any possibility of disturb.
The invention also provides a method of reading a ferroelectric memory cell which senses the capacitance difference between memory cells in different logic states.
The invention also provides a memory cell in which the ferroelectric elements are capacitors, which memory cell can be read without switching the ferroelectric capacitors.
The invention also provides a novel bit line driver for a ferroelectric memory which drives the bit line to a voltage of a volt or less, and preferably less than half a volt.
The invention also provides a novel sense amplifier for use in a ferroelectric memory, which sense amplifier includes three bit line inputs, two of which are inputs from dummy bit lines.
The invention also provides a method of operating a ferroelectric memory having a pair of dummy cells in which the logic states of the dummy cells are alternated, which avoids imprinting the dummy cells.
The invention also provides a ferroelectric memory in which the bit lines are partitioned.
The invention provides a ferroelectric, non-volatile memory comprising: a plurality of pairs of parallel bit lines and a plurality of memory cells, each memory cell associated with one of the pairs of bit lines, each memory cell comprising: a first ferroelectric capacitor having a first electrode and a second electrode, a second ferroelectric capacitor having a first electrode and a second electrode, a first transistor having a gate, and a second transistor having a gate; wherein in each memory cell the first transistor is connected between the first electrode of the first capacitor and one of the bit lines in the associated bit line pair, the second transistor is connected between the first electrode of the second capacitor and the other of the bit lines in the associated bit line pair; the memory further including a plurality of drive lines and a drive line transistor associated with each of the drive lines, the drive line transistor including a gate, the drive lines being parallel to the bit lines, each of the drive lines connected to the second electrode of at least one of the capacitors in at least one of the memory cells via the drive line transistor, each of the drive lines connected to two or less of the memory cells; the memory further including a word line perpendicular to the bit line pairs and the drive lines, and the gates of the first transistor, the second transistor and the drive line transistor connected to the word line. Preferably, each of the drive lines is connected to the second electrode of the first capacitor and the second electrode of the second capacitor in only one of the memory cells. Preferably, there is one of the drive lines associated with each of the cells, and the drive line is located between the bit lines in the bit line pair associated with the cell with which the drive line is associated. Preferably, each of the drive lines is connected to the second electrode of the first capacitor and the second electrode of the second capacitor in two of the memory cells. Preferably, the bit lines are complementary and each of the memory cells is a one-bit memory cell. Preferably, one of the two memory cells is a two-bit memory cell and the other of the two memory cells is a one-bit memory cell including a dummy capacitor, and the bit line connected to the dummy capacitor is a dummy bit line. Preferably, the bit lines are top level bit lines and there are a plurality of the memory cells divided into a first group and a second group, the memory further including a first group select transistor having a gate, a second group select transistor having a gate, a first group select line, a second group select line, a first second level bit line, and a second second level bit line, and wherein the first group select transistor is connected between the top level bit line and the first second level bit line, the second group select transistor is connected between the top level bit line and the second second level bit line, the first group select line is connected to the gate of the first group select transistor, and the second group select line is connected to the gate of the second group select transistor. Preferably, the memory further includes a bit line driver circuit for driving the bit line to a voltage that is one-third or less of the high voltage of the memory. Preferably, each of the memory cells is a two-bit memory cell. Preferably, one of the pairs of bit lines are dummy bit lines, the memory cell associated with the dummy bit line pair is a dummy cell, and the drive line connected to the dummy cell is a dummy drive line. Preferably, the dummy bit lines are complementary. Preferably, during a first memory cycle, the logic state of the first capacitor in the dummy cell is a logic xe2x80x9c0xe2x80x9d and the logic state of the second capacitor in the dummy cell is a logic xe2x80x9c1xe2x80x9d, and during a second memory cycle the logic state of the first capacitor in the dummy cell is a logic xe2x80x9c1xe2x80x9d and the logic state of the second capacitor in the dummy cell is a logic xe2x80x9c0xe2x80x9d. Preferably, the memory further includes a sense amplifier having three-bit line inputs, two of the inputs connected to the pair of dummy bit lines. Preferably, there are two of the drive lines and two of the drive line transistors associated with each of the cells, one of the two drive lines connected to the second electrode of the first capacitor via a first one of the two drive line transistors and the other of the two drive lines connected to the second electrode of the second capacitor via a second one of the two drive line transistors. Preferably, the pair of bit lines associated with each of the cells are complementary. Preferably, each of the cells is a two-bit cell. Preferably, one of the cells includes a dummy capacitor. Preferably, the cell that includes a dummy capacitor is a dummy cell having a pair of dummy bit lines connected to a pair of dummy capacitors and a pair of dummy drive lines connected to the pair of dummy capacitors. Preferably, during a first memory cycle, the logic state of the first capacitor in the dummy cell is a logic xe2x80x9c0xe2x80x9d and the logic state of the second capacitor in the dummy cell is a logic xe2x80x9c1xe2x80x9d, and during a second memory cycle the logic state of the first capacitor in the dummy cell is a logic xe2x80x9c1xe2x80x9d and the logic state of the second capacitor in the dummy cell is a logic xe2x80x9c0xe2x80x9d. Preferably, there are a plurality of word lines, each of the word lines associated with a different row of memory cells with the gates of each of the transistors in each of the memory cells in a row of memory cells connected to the word line associated with the row; and the memory includes a drive line driver circuit connected, via the drive line, to the first and second capacitors in at least one of the memory cells in each of a plurality of the rows.
In another aspect, the invention provides a ferroelectric, non-volatile memory comprising a pair of complementary bit lines, a drive line located between and parallel to the complementary bit lines, a word line perpendicular to the bit lines and drive line, and a memory cell comprising: a first ferroelectric capacitor, a second ferroelectric capacitor, a first transistor, a second transistor, and a drive line transistor; wherein the first transistor is connected between the first capacitor and one of the complementary bit lines, the second transistor is connected between the second capacitor and the other of the complementary bit lines, and the drive line transistor is connected between at least one of the capacitors and the drive line.
In a further aspect, the invention provides a ferroelectric, non-volatile memory wherein the bit lines and drive lines are partioned. In the embodiment where the bit lines are partioned, there are is hierarchy of bit lines, with each higher hierarchical level connected to a plurality of bit lines at the next lower level via transistors controlled by group select signals. Preferably, there are top level bit lines and there are a plurality of memory cells divided into a first group and a second group, the memory further including a first group select transistor having a gate, a second group select transistor having a gate, a first group select line, a second group select line, a first second level bit line, and a second second level bit line, and wherein the first group select transistor is connected between the top level bit line and the first second level bit line, the second group select transistor is connected between the top level bit line and the second second level bit line, the first group select line is connected to the gate of the first group select transistor, and the second group select line is connected to the gate of the second group select transistor.
In another aspect, the invention provides a ferroelectric, non-volatile memory comprising: a first bit line; a second bit line parallel to the first bit line; a drive line located between and parallel to the first and the second bit lines; a plurality of memory cells, each memory cell comprising: a first ferroelectric capacitor, a second ferroelectric capacitor, a first transistor, a second transistor, and a third transistor, each having a gate; wherein the first transistor is connected between the first capacitor and the first bit line, the second transistor is connected between the second capacitor and the second bit line, and the third transistor is connected between the capacitors and the drive line; a plurality of word lines, each of the word lines associated with a different row of memory cells with the gates of each of the transistors in each of the memory cells in a row of memory cells connected to the word line associated with the row; and a drive line driver circuit connected, via the drive line, to the first and second capacitors in at least one of the memory cells in each of a plurality of the rows.
In still another aspect, the invention provides a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric element, the polarization of the ferroelectric element corresponding to the data stored therein, the memory also including a signal generator providing a read signal, the improvement wherein the memory further comprises a bit line driver circuit responsive to the read signal for driving the bit line to a voltage of no more than one volt.
In still another aspect, the invention provides a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric element, the polarization of the ferroelectric element corresponding to the data stored therein, the memory also including a signal generator providing a read signal, the improvement wherein two of the bit lines are complementary dummy bit lines and one of the bit lines is not a dummy bit line; the memory further comprises: a sense amplifier having a first bit line input connectable to the bit line that is not a dummy bit line, a second bit line input connectable to a first one of the dummy bit lines, and a third bit line input connectable to a second one of the dummy bit lines.
In yet another aspect, the invention provides a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric element, the polarization of the ferroelectric element corresponding to the data stored therein, the improvement wherein the bit lines are top level bit lines and there are a plurality of memory cells divided into a first group and a second group; the memory further including a first group select transistor having a gate, a second group select transistor having a gate, a first group select line, a second group select line, a first second level bit line, and a second second level bit line, and wherein the first group select transistor is connected between the top level bit line and the first second level bit line, the second group select transistor is connected between the top level bit line and the second second level bit line, the first group select line is connected to the gate of the first group select transistor, and the second group select line is connected to the gate of the second group select transistor.
The invention also provides a method of operating a ferroelectric, non-volatile memory comprising a plurality of memory cells, each memory cell including a memory cell ferroelectric element, the method comprising: electrically isolating each of the memory cell ferroelectric elements from all other memory cell ferroelectric elements. Preferably, the memory cell ferroelectric element is a ferroelectric capacitor.
In another aspect, the invention provides a method of operating a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line pair coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a pair of ferroelectric memory elements, the polarization of each of the ferroelectric memory elements corresponding to the data stored therein; the method comprising: electrically isolating each of the ferroelectric memory element pairs from all other ferroelectric memory element pairs. Preferably, each of the drive lines is coupled to the memory cells along a column and each of the memory cells in said column includes a plurality of transistors, a first one of the transistors connected between a first one of the ferroelectric capacitors and a first one of the bit lines in the bit line pair associated with said column, a second one of the transistors connected between a second one of the ferroelectric capacitors and a second one of the bit lines in the bit line pair associated with said column, and a third one of the transistors connected between at least one of the ferroelectric capacitors and the drive line associated with the column, and electrically isolating comprises keeping the first, second and third transistors associated with each memory cell in said column off except when the associated memory cell is selected to be addressed, and selecting only one memory cell in the column at a time. Preferably, the third transistor is connected between the first ferroelectric capacitor and a first associated drive line and each of the memory cells includes a fourth transistor connected between the second ferroelectric capacitor and a second associated drive line, and the keeping comprises keeping the fourth transistor in the column off except when the associated memory cell is selected to be addressed. Preferably, the isolating includes writing to one of the memory cells while maintaining the isolation. Preferably, the writing comprises writing a first predetermined logic state during a first time period and writing a second predetermined logic state during a second time period. Preferably, the writing comprises writing a first predetermined logic state to both of the ferroelectric memory elements in one of the pairs of elements and then writing a second predetermined logic state to any of the ferroelectric elements in the pair for which the data applied to the memory requires that it be in a state other than the first predetermined state. Preferably, the isolating includes reading one of the memory cells while maintaining the isolation. Preferably, the reading comprises a destructive read out method. Preferably, the reading comprises a non-destructive read out method.
In a further aspect, the invention provides a method of operating a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a pair of ferroelectric memory elements, the polarization of each of the ferroelectric memory elements corresponding to the data stored therein; the method comprising: electrically isolating each of the ferroelectric memory element pairs from all other ferroelectric memory element pairs; applying a single read pulse to a memory cell; and sensing the logic state of the memory cell after the single read pulse. Preferably, the method further comprises applying a rewrite pulse to the memory cell.
In another aspect, the invention provides a method of operating a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric memory element, the polarization of the ferroelectric memory element corresponding to the data stored therein, the method comprising: applying a read pulse voltage of no more than one volt to a memory cell; and sensing the logic state of the memory cell after the read pulse. Preferably, the read pulse is one-half volt or less.
In still a further aspect, the invention provides a method of reading a ferroelectric, non-volatile memory of the type having at least twenty-five memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric memory element, the polarization of the ferroelectric memory element corresponding to the data stored therein, the method comprising: reading one of the memory cells connected to a selected drive line; and electrically connecting no more than four of the ferroelectric memory elements to the selected drive lines during the step of reading.
In yet another aspect, the invention provides a method of reading a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric memory element, the capacitance state of the ferroelectric memory element corresponding to the data stored therein, the method comprising: electrically connecting a selected memory cell to a selected bit line; and providing a data output signal corresponding to the capacitance state of the ferroelectric memory element.
In still another aspect, the invention provides a method of reading a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric memory element, the polarization of the ferroelectric memory element corresponding to the data stored therein, the method comprising: electrically connecting a selected memory cell to a selected bit line; applying an electrical charge to the bit line; without switching the ferroelectric memory element of the selected cell, absorbing in the element an amount of the charge dependent on the polarization state of the ferroelectric memory element; and sensing the voltage on the selected bit line and providing a data output signal corresponding to the polarization state of the ferroelectric memory element.
In yet another aspect, the invention provides a method of reading a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric capacitor, the polarization of the ferroelectric memory element corresponding to the data stored therein, the method comprising: selecting one of the ferroelectric memory cells; and reading the capacitor in the selected memory cell without changing the ferroelectric polarization state of the capacitor. Preferably, the step of reading comprises sensing the capacitance of the ferroelectric capacitor.
The invention also provides, in a further aspect, a method of operating a ferroelectric, non-volatile memory of the type having a plurality of memory cells arranged in rows and columns, each column comprising a bit line coupled to memory cells along the column, the bit lines including a first dummy bit line connected to a first dummy memory cell, each row comprising a word line coupled to cells along the row, the memory also including a plurality of drive lines distinct from the bit and word lines, each memory cell coupled to a corresponding drive line, each memory cell comprising a ferroelectric memory element, the polarization of the ferroelectric memory element corresponding to the data stored therein, the method comprising writing a first logic state to the first dummy memory cell in a first memory cycle and writing a second logic state to the first dummy memory cell in a second memory cycle.
In yet another aspect, the invention provides a method of selecting a memory cell in a ferroelectric, non-volatile memory having a plurality of memory arrays, each memory array having a plurality of memory cells arranged in rows and columns; selecting one of the plurality of arrays; and selecting a memory cell in the selected array. Preferably, the selecting comprises selecting a pair of memory cells while electrically isolating the selected memory cells from all other memory cells in the memory. Preferably, the selecting comprises selecting a single memory cell while electrically isolating the selected memory cell from all other memory cells in the memory.
In still a further aspect, the invention provides a method of writing to a ferroelectric, non-volatile memory, the method comprising: selecting a single memory cell used in complementary mode in the memory; and writing data to the selected memory cell without electrically connecting it to any non-selected memory cell in the memory.
In still another aspect, the invention provides a method of writing to a ferroelectric, non-volatile memory, the method comprising: selecting a single memory cell in the memory; and writing data to the selected memory cell without electrically connecting it to any non-selected memory cell in the memory.
In yet a further aspect, the invention provides a method of reading a ferroelectric, non-volatile memory, the method comprising: selecting a single memory cell used in complementary mode in the memory; and reading the selected memory cell without electrically connecting to any non-selected memory cell in the memory.
In yet another aspect, the invention provides a method of reading a ferroelectric, non-volatile memory, the method comprising: selecting a single memory cell in the memory; and writing data to the selected memory cell without electrically connecting it to any non-selected memory cell in the memory.
The invention for the first time provides a ferroelectric, non-volatile memory which is competitive with DRAMs and SRAMs with respect to speed, reliability, and density. Numerous other features, objects and advantages of the invention will become apparent from the following description when read in conjunction with the accompanying drawings.